1. Field of the Invention
The present invention relates to a method of forming multilevel interconnects that are used to interconnect semiconductor devices. More particularly, the present invention relates to a method of forming a dual damascene structure.
2. Description of the Related Art
Dual damascene process is an ingenious technology that embeds metallic interconnects in an isolation layer. The method of forming a dual damascene structure includes forming an isolation layer on a dielectric layer at first, and then planarizing the isolation layer. The isolation layer is etched to form horizontal trenches and vertical vias according to the predetermined metallic line pattern and positions of via holes. A metallic layer is deposited over the dielectric layer to fill the horizontal trenches and the vertical vias, and then metallic lines and vias are formed simultaneously. Subsequently, a chemical-mechanical polishing (CMP) step is performed to planarize the device surface. The dual damascene structure thus is completed. In contrast with the conventional process, which forms vias and metallic lines separately, the dual damascene process forms vias and metallic lines simultaneously. Therefore, overlay errors or process bias arising from mask misalignments does not happened, and the reliability of devices can be improved. With the trend toward high integration density, dual damascene process is widely adopted in the semiconductor industry.
FIGS. 1A through 1E are schematic, cross-sectional views showing a conventional fabricating method of a dual damascene structure.
In FIG. 1A, a dielectric layer 100 having a metallic layer 102 therein is provided. An inter-metal dielectric (IMD) layer 104 is formed on the dielectric layer 100 and the metallic layer 102. The inter-metal dielectric layer 104 is planarized by chemical-mechanical polishing. To prevent reflection by the metallic layer 102. An antireflection layer 105 is formed on the inter-metal dielectric layer 104. The anti-reflection layer 105 is used to prevent reflection by the metallic layer 102.
In FIG. 1B, a first patterned photoresist layer 110 is formed on the anti-reflection layer 105. The first patterned photoresist layer 110 is used as an etching mask. The anti-reflection layer 105 and the inter-metal dielectric layer 104 are patterned to form an opening 108 in the inter-metal dielectric layer 104 until the metallic layer 102 is exposed. The first photoresist layer 110 is removed.
In FIG. 1C, a second patterned photoresist layer 112 is formed on the antireflection layer 105. The second patterned photoresist layer 112 is used as an etching mask.
In FIG. 1D, the anti-reflection layer 105 and the inter-metal dielectric layer 104 are patterned again to form trenches 114 and 116. The trench 114 is formed above the metallic layer 102. A dual damascene structure opening 118 is formed by the trench 114 together with the residual opening 108a. The second photoresist layer 112 is removed.
In FIG. 1E, a conductive layer (not shown) is deposited over the dielectric layer 100 to fill the dual damascene structure opening 118 and the trench 116. The conductive layer is planarized to form a dual damascene structure 120 and a metallic line 122 by chemical mechanical polishing. Conventionally, the material of the conductive layer can be aluminum or tungsten with a titanium/titanium nitride composite layer underneath used as a barrier layer/glue layer.
In the conventional process described in FIGS. 1A through 1E, no any other layers serve as an etching stop layer while etching the inter-metal dielectric layer 104 to form the trenches 114 and 116. Consequently, it is difficult to control the depth of the trenches 114 and 116. Hence, ultimate electrical properties of devices can vary considerably.
FIGS. 2A through 2E are schematic, cross-sectional views showing the other conventional fabricating method of a dual damascene structure.
In FIG. 2A, a dielectric layer 200 having a first metallic layer 202 therein is provided. A dielectric layer 204a is formed on the dielectric layer 200. The dielectric layer 204a is planarized to reach a thickness the same as the predetermined depth of a via hole. A silicon nitride layer 206, which is used as an etching stop layer, is formed on the dielectric layer 204a.
In FIG. 2B, a first patterned photoresist layer 210 is formed on the silicon nitride layer 206. The first patterned photoresist layer 210 is used as an etching mask. The silicon nitride layer 206 is etched to form an opening 208. The opening 208 is formed above the location where a via hole is desired to locate in. The opening 208 is formed just above the metallic layer 202.
In FIG. 2C, a second dielectric layer 204b and an anti-reflection layer 205 are formed in order over the dielectric layer 200. The thickness of the dielectric layer 204b is same as the predetermined thickness of the second metallic layer (metallic line) in a dual damascene structure.
In FIG. 2D, a patterned photoresist layer 212 is formed on the anti-reflection layer 205. The patterned photoresist layer 212 is used as an etching mask. The dielectric layer 204b is etched to form trenches 214a and 216. The silicon nitride layer 206 is used as an etching stop layer. The dielectric layer 204a is etched to form an opening 214b that exposes the first metallic layer 202. A dual damascene structure opening 214 is formed by the trench 214a together with the opening 214b.
In FIG. 2E, the second patterned photoresist layer 212 is removed. A conductive layer (not shown) is deposited over the dielectric layer 200 to fill the opening 214 and the trench 216. The conductive layer is planarized to form a dual damascene structure 220 and a metallic line 222. Typically, the material of the conductive layer can be aluminum or tungsten with a titanium/titanium nitride composite layer underneath serving as a barrier layer/glue layer.
In the conventional process described in FIGS. 2A through 2E, it is necessary to select a material, which provides a high selectivity of etching rate compared with the dielectric layer 204a, for the etching stop layer 206. Conventionally, the silicon oxide is used as the dielectric layer 204a and silicon nitride is used as the etching stop layer 206. The etching selectivity of etching step must be good enough to control the depth of trench 216 while etching the silicon oxide dielectric layer 204a to form the opening 214b. However, the dielectric constant of silicon nitride is higher than the dielectric constant silicon oxide. It can lead to a higher parasitic capacitance. Moreover, a silicon nitride etching stop layer 206 can create internal stress large enough to cause cracks and peeling at the interface between the silicon oxide dielectric layer 204a and the silicon nitride etching stop layer. In some cases, the use of high temperature in subsequent processing operations may give rise to serious distortion of the dielectric layer 200 that may cause some problems in the following photolithography process.